Field of the Invention
The invention relates to a method for reducing congestion regions in layout area of an integrated circuit (IC), and more particularly to a method for reducing congestion regions in layout area of an IC by simultaneously redistributing the cell resources and the routing resources.
Description of the Related Art
In recent years, the development process of integrated circuits (ICs) such as super larger scale integrated circuits (LSIs) has generally utilized computer assisted design (CAD). According to a development process based on CAD, abstract circuit data, which corresponds to functions of an integrated circuit to be developed, is defined by using a so-called hardware description language (HDL), and the defined circuit is used to form a concrete circuit structure to be mounted on a chip.
Before the IC chips are manufactured (or implemented), the placements and the layout areas of the IC chips are considered first so as to determine the die size of each IC chip. In general, the die size will affect the manufacturing cost for the IC chip. Therefore, it is desirable to optimize the placements of an IC chip for minimizing the layout area of the IC chip.